Many III-V transistor technologies are under investigation as candidates to eventually replace silicon transistor technology. For many III-V material systems, metal-oxide-semiconductor (MOS) high electron mobility transistor (HEMT) architectures are attractive. For such a device, gate-recessing and source/drain regrowth are two manufacturing alternatives typically practiced. For a gate recess technique, a starting material includes a complete epitaxial semiconductor stack that includes a heavily doped (e.g., N+) source/drain layer(s). A portion of the epitaxial stack including the source/drain layers is then etched to form a recess into which a gate electrode or gate stack (including a gate insulator) is disposed in close proximity to a channel layer of the epitaxial stack. In contrast, for a source/drain regrowth technique, a gate electrode or gate stack or dummy gate (which will eventually be replaced via a replacement gate electrode) is first disposed on a starting material that includes an epitaxial stack lacking the heavily doped source/drain layer(s). After gate formation, heavily doped source/drain regions are then epitaxially grown around the gate electrode.
One promising III-V transistor technology is based on III-nitrides (III-N), commonly referred to as GaN-based devices. While GaN MOS-HEMTs, may in theory be formed by either the gate-recessing or source/drain regrowth technique, practically speaking, gate-recessing is extremely difficult in GaN-based material stacks because simple wet etching solutions are not viable due to strong chemical bonds of GaN and no known dry etch stop chemistry is considered reliable. Gate-recessed MOS-HEMTs have the advantage of ultra-scaled gate-to-Source and gate-to-Drain distance, enabling the lowest possible transistor on resistance, access resistance, hence high transconductance and high fT/fMax. For these reasons, gate-recessed GaN devices today are based on timed dry etch. Such an approach requires precise control of process parameters, and the epitaxial layer thickness has to be precisely known ahead of time. This has negative implications for manufacturability and reliability as slight over etch results in damage to the GaN channel (e.g., loss of sheet charge, carrier mobility, increase in interface trap states, etc.) and under etch also adversely affects device parametrics (e.g., poor transconductance, high on-state resistance (RON), etc).
Because of the practical difficulty in the gate-recessed approach, the vast majority of state-of-the-art GaN HEMT and MOS-HEMT research focuses on regrowth of source and drain post formation of the gate stack. However, regrowth of an N+ GaN source and drain region also poses many technical challenges. For example, the Metal Organic Vapor Phase Epitaxy (MOVPE) growth temperature of N+ GaN is over 1000° C. Such a high temperature precludes the formation of high-k gate dielectric prior to source/drain regrowth because various gate dielectrics formed by atomic layer deposition (ALD), such as HfO2, crystallize and otherwise degrade. Similarly, various metal gate electrode materials desirable for a particular work function also diffuse and degrade at such high temperatures. While the Molecular Beam Epitaxy (MBE) growth temperature of N+ GaN is less than 1000° C., because MBE is a line-of-sight deposition technique, “shadow” effects result in suboptimal (e.g., high resistance) and inconsistent device performance. These challenges have therefore generally required the use of a more complex replacement gate process to affect a source/drain regrowth technique in GaN-based devices.
Recessed gate GaN MOS-HEMTs employing highly N+ doped III-N layers as a contact layer to form low resistance ohmic contacts to source/drain metal are an attractive device architecture amenable to fabricating self-aligned gate structures and ultra-scaled spacer dielectrics to enable ultra low access resistance from source and drain to the channel. The ability to achieve low access resistance coupled with the ability to scale the gate length to deep submicron regime is important to obtaining low RON. Moreover, as a gate last process, the recessed gate technique offers many advantages including making possible a whole host of temperature sensitive high-k and metal gate solutions. These benefits along with the recessed-gate technique being able to scale the gate dielectric thickness aggressively make a recessed gate GaN-based MOS-HEMT architecture highly advantageous. Epitaxial stack materials for manufacturable gate-recessing techniques are therefore advantageous.